hardware

hardware

RF Filter Design for ESP32-S3, Part 4: Track Keepout and Crosstalk Isolation

In this post, we demonstrate why traces routed beneath an RF path degrade an ESP32-S3 filter even when the schematic says they’re isolated, and how Track Keepout in Altium, CST re-simulation and component re-tuning restore isolation without giving up S₁₁ matching.

hardware

RF Filter Design for ESP32-S3, Part 3: Real Components and EMI Analysis

Ideal components cannot predict the losses and resonances of a fabricated RF filter. Part 3 evaluates frequency-dependent Murata 0402 models, selects practical component values, and transfers them into the CST 3D EM model to analyze S₁₁, EM fields, and power loss as a basis for EMI optimization.

hardware

RF Filter Design for ESP32-S3, Part 2: PCB Effects and EM Co-Simulation

An ideal RF filter changes once PCB geometry is included. Part 2 imports the Altium layout into CST, uses EM co-simulation to expose trace, pad, and coupling parasitics, and re-optimizes the component values to restore the target S₁₁ response.

hardware

RF Filter Design for ESP32-S3, Part 1: The Ideal Filter and First Layout

An ESP32-S3 RF filter that passes simulation can still fail on the fabricated board. Part 1 of this series builds the foundation: a CLC PI filter designed in CST Studio Suite, optimized with CMA-ES across the 2.4 GHz Wi-Fi channels, and carried into a controlled-impedance Altium layout.